Scott Lerner

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Scott Lerner

Education

PhD in Electrical Engineering expected graduation mid-2019

Drexel University, Philadelphia, PA.

B.S. in Electrical Engineering, 2014

Drexel University, Philadelphia, PA.

B.S. in Computer Engineering, 2014

Drexel University, Philadelphia, PA.

Research Interests

My research interests span the areas of circuits and systems, computer architecture, cross-layer techniques, and emerging computing systems. I have specific interests in workload-awareness, machine learning, multi-core architectures, and internet-of-things.

Curriculum Vitae

Scott Lerner CV (Jun 2018)

Selected Publications

  1. S. Lerner, V. Pano, B.Taskin, NoC Router Lifetime Improvement using Per-Port Router Utilization, Proceedings of the International Symposium on Circuit and Systems (ISCAS) 2018.
  2. V. Pano, S. Lerner, B.Taskin, Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement, Proceedings of the International Symposium on Circuit and Systems (ISCAS) 2018.
  3. R.Kuttappa, L. Fillipini, S. Lerner, and B.Taskin, Stability of Rotary Traveling Wave Oscillators under Process Variations and NBTI, presented at International Symposium on Circuits and Systems (ISCAS), May 2017.
  4. S. Lerner, B.Taskin, WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS, presented at International Symposium on VLSI (ISVLSI), July 2017.
  5. S. Lerner, E. Leggett, and B.Taskin, Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers, presented at System Level Interconnect Prediction (SLIP) 2017.
  6. S. Lerner, B.Taskin, BSST-DME: Slew Merging Region Propagation for Bounded CTS, submitted to International Conference on Computer Aided Design (ICCAD) 2017.
  7. S. Lerner, B.Taskin, Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors, Proceedings of the International Symposium on Quality Electronic Design, March 2017.
  8. C. Sitik, W. Liu, S. Lerner, E. Salman, and B. Taskin, An Improved Methodology for Low Voltage Gated Clock Tree Synthesis, submitted to International Symposium on Physical Design (ISPD) 2017.
  9. S. Nilakantan, S. Lerner, M. Hempstead and B. Taskin, Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation, Presented at the IEEE International Conference on VLSI Design (VLSIDESIGN), January 2015. Best Paper Nominee
  10. C. Sitik, S. Lerner, and B. Taskin, Timing Characterization of Clock Buffers for Clock Tree Synthesis, Paper presented at ICCD, October 2014.

Poster Presentations

  1. S. Lerner, B. Taskin Enhancements in Low Voltage and High Performance Clock Distribution Networks, Poster presented at SRC Innovation and Intelligent Internet of Things, Nov. 2016.
  2. A. Milani, S. Lerner, B. Taskin High-Frequency Clock Tree Synthesis, Poster presented at Drexel STAR Symposium, Aug. 2016.
  3. R. Farnesi, S. Lerner, B. Taskin Internal Node Relaxation for Clock Tree Synthesis, Poster presented at Drexel STAR Symposium, Aug. 2016.
  4. S. Lerner, B. Taskin Workload-Aware EDA, Presentation given at IEEE CE Graduate Symposium, Feb. 2016.
  5. S. Lerner, V. Pano, and B. Taskin, Wireless Network-on-Chip, Poster to be presented at Mid-Atlantic ASEE, November 2014
  6. S. Lerner, Arduino Robotics in the Classroom, Poster to be presented at Mid-Atlantic ASEE, November 2014
  7. Scott Lerner, and Baris Taskin, Low-Power Clock Network Designs, Poster presented at IEEE Design Automation Conference, June 2014
  8. S. Lerner, C. Sitik, and B. Taskin, Low Swing Clocking Algorithm for 20nm FinFET Technology, Poster presented at Upsilon Pi Epsilon Research Reception, February 2014.
  9. S. Lerner, C. Sitik, and B. Taskin, Sub-45nm Interconnect Modeling, Poster presented at Drexel IEEE Graduate Forum, February 2014.
  10. S. Lerner, R. Welliver, B. Derveni, C. Schoenfield, I. Yilmaz, MotionExplorer, A Leap Motion-Controlled Electric Wheelchair, presented at Philly Codefest, February 2014.
  11. C. Sitik, S. Lerner, and B. Taskin, Low-Power/High-Performance Clock Network Design for Microprocessors, Poster presented at Upsilon Pi Epsilon Research Reception, February 2013.

Awards

  1. Frank and Agnes Seaman Endowed Fellowship, 2016
  2. NSF Graduate Research Fellowship Program (GRFP), 2015
  3. National Defense Science & Engineering Graduate (NDSEG) Fellowship (declined), 2015
  4. Nihat Bilgutay Award, 2015
  5. TCVLSI Travel Award, 2015
  6. NSF Research Experience for Undergraduate (REU) recipient 2014
  7. A. Richard Newton Young Fellow Award to attend to IEEE/ACM DAC 2014, 2015, 2016, 2017
  8. Dean's Choice Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
  9. NextFab Innovation Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
  10. Doctor Thomas Moore Endowed Grant 2014
  11. Dean's List, 2009, 2010, 2011, 2012, 2013, 2014

Selected Projects

  1. Leap Motion-Controlled Electric Wheelchair, Philly Codefest, February 2014 Dean's Choice Award

Contact Information

Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia
Pennsylvania 19104

Phone: (863) 307-6194
Fax: (215) 895-1695
Email: spl29@drexel.edu

Retrieved from "https://research.coe.drexel.edu/ece/vlsi/index.php?title=Scott_Lerner&oldid=3681"