Scott Lerner

Scott Lerner

Education

PhD in Electrical Engineering expected graduation mid-2019

Drexel University, Philadelphia, PA.

B.S. in Electrical Engineering, 2014

Drexel University, Philadelphia, PA.

B.S. in Computer Engineering, 2014

Drexel University, Philadelphia, PA.

Research Interests

My research interests span the areas of circuits and systems, computer architecture, cross-layer techniques, and emerging computing systems. I have specific interests in workload-awareness, machine learning, multi-core architectures, and internet-of-things.

Curriculum Vitae

Scott Lerner CV (Dec 2018)

Journals

1. S. Lerner and B.Taskin, “Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis”, in

IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2874572

1. S. Lerner, I. Yilmaz, and B.Taskin, “Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors”,

in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2878664

1. S. Lerner, and B.Taskin, “Workload-Aware ASIC Design Considering Lithography Information”, in preparation for

submission, 2019.

Papers

1. S. Lerner and B.Taskin, “Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis”, Proceedings of the IEEE International Green and Sustainable Computing (IGSC) Conference, Oct. 2018.
2. S. Lerner, V. Pano, and B.Taskin, “NoC Router Lifetime Improvement using Per-Port Router Utilization”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2018.
3. V. Pano, S. Lerner, and B.Taskin, “Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2018.
4. R.Kuttappa, L. Fillipini, S. Lerner, and B.Taskin, “Stability of Rotary Traveling Wave Oscillators under Process Variations and NBTI”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2017.
5. S. Lerner and B.Taskin, “WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS”, Proceedings of the International Symposium on VLSI (ISVLSI), Jul. 2017.
6. S. Lerner, E. Leggett, and B.Taskin, “Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers”, Proceedings of the System Level Interconnect Prediction (SLIP), Jun. 2017.
7. S. Lerner and B.Taskin, “Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors”, Proceedings of the International Symposium on Quality Electronic Design (ISQED), Mar. 2017.
8. S. Nilakantan, S. Lerner, M. Hempstead, and B. Taskin, “Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation”, Nominated for best paper at the IEEE International Conference on VLSI Design (VLSID), Jan. 2015.
9. C. Sitik, S. Lerner, and B. Taskin, “Timing Characterization of Clock Buffers for Clock Tree Synthesis”, Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2014.

Presentations

1. “Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis”, International Green and Sustainable Computing Conference, Pittsburgh, PA, October 2018.
2. “NoC Router Lifetime Improvement using Per-Port Router Utilization”, International Symposium on Circuit and Systems, Florence, Italy, May 2018.
3. “Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement”, International Symposium on Circuit and Systems, Florence, Italy, May 2018.
4. “WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS”, International Symposium on VLSI, Bochum, Germany, July 2017.5. “Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers”, System Level Interconnect Prediction, Austin, Texas, June 2017.
5. “Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors”, International Symposium on Quality Electronic Design, Santa Clara, California, March 2017.

1. Enhancements in Low Voltage and High Performance Clock Distribution Networks, SRC Innovation and Intelligent Internet of Things, November 2016.
2. High-Frequency Clock Tree Synthesis, Drexel STAR Symposium, August 2016.
3. Internal Node Relaxation for Clock Tree Synthesis, Drexel STAR Symposium, August 2016.
4. Workload-Aware EDA, IEEE CE Graduate Symposium, February 2016.
5. Wireless Network-on-Chip, Mid-Atlantic ASEE, November 2014
6. Arduino Robotics in the Classroom, Mid-Atlantic ASEE, November 2014
7. Low-Power Clock Network Designs, IEEE Design Automation Conference, June 2014
8. Low Swing Clocking Algorithm for 20nm FinFET Technology, Upsilon Pi Epsilon Research Reception, February 2014.
9. Sub-45nm Interconnect Modeling, Drexel IEEE Graduate Forum, February 2014.
10. MotionExplorer, A Leap Motion-Controlled Electric Wheelchair, Philly Codefest, February 2014.
11. Low-Power/High-Performance Clock Network Design for Microprocessors, Upsilon Pi Epsilon Research Reception, February 2013.

Awards

1. IGSC Best Presentation Nominee, 2018
2. IGSC Travel Award, 2018
3. Weggel Family Fellowship, 2018
4. Frank and Agnes Seaman Endowed Fellowship, 2016
5. NSF Graduate Research Fellowship Program (GRFP), 2015-2018
6. National Defense Science & Engineering Graduate (NDSEG) Fellowship (declined), 2015
7. Nihat Bilgutay Award, 2015
8. TCVLSI Travel Award, 2015
9. NSF Research Experience for Undergraduate (REU) recipient 2014
10. A. Richard Newton Young Fellow Award 2014, 2015, 2016, 2017, 2018
11. Dean's Choice Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
12. NextFab Innovation Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
13. Doctor Thomas Moore Endowed Grant 2014
14. Dean's List, 2009-2014

Selected Projects

1. Leap Motion-Controlled Electric Wheelchair, Philly Codefest, February 2014 Dean's Choice Award

Contact Information

Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia
Pennsylvania 19104

Phone: (863) 307-6194
Fax: (215) 895-1695
Email: spl29@drexel.edu