Can Sitik

Can Sitik

Education

Ph.D. in Computer Engineering, 2011 - Present

Drexel University, Philadelphia, Pennsylvania, USA

M.S. in Computer Engineering, 2013

Drexel University, Philadelphia, Pennsylvania, USA

B.S. in Electrical and Electronics Engineering, 2011

Middle East Technical University(METU), Ankara, Turkey

Research Interests

• Low Swing Clock Tree Synthesis
• Pre- and Post-Si Power and Timing Modeling
• Clock Mesh Synthesis, clock mesh benefits
• Electronic Design Automation(EDA) for VLSI, what is EDA?
• Clock Network Design with FinFETs

Curriculum Vitae

Can Sitik CV (Feb 2015)

Publications

Journals

1. Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ACM Journal of Emerging Technologies in Computing Systems (JETC), Vol. 12, No. 2, Article 13, August 2015.
2. Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", Elsevier Integration, The VLSI Journal, Vol. 47, No. 3, pp. 356--364, June 2014.

Conferences

1. Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the Proceedings of Semiconductor Research Corporation (SRC) TECHCON, September 2015.
2. Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2015, pp. 301--306.
3. Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2015, pp. 283--288.
4. Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2015, pp. 1442--1445.
5. Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2014, pp. 230--236.
6. Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2014, pp. 498--503.
7. Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE), June 2013, pp. 28--31.
8. Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013, pp. 209--214.
9. Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013, pp. 49--54 Best Paper Nominee.
10. Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley, March 2013.
11. Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2012, pp. 201--206.

Google Scholar Page

Teaching

• ECE-C671: EDA for VLSI I (Winter 2015)
• ECE-C304: Design with Microcontrollers (Winter 2012-14, Summer 2012,13)
• ECE-C302: Digital Systems Projects (Fall, Spring 2013)
• ENGR-231: Linear Engineering Systems (Spring, Fall 2012)
• ECE-E421: Advanced Electronics I (Fall 2011)

Please refer to my Weekly Schedule to ask for an appointment

Contact Information

Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia, PA 19104

Email: as3577@drexel.edu

Linkedin: A. Can Sitik