Publications

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Conferences

  1. Leo Filippini and Baris Taskin, "Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2016.
  2. Karthik Sangaiah, Mark Hempstead and Baris Taskin, "Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling", Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2015, pp. 365--372.
  3. Leo Filippini, Emre Salman, Baris Taskin, "A Wirelessly Powered System with Charge Recovery Logic", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2015, pp. 505--510.
  4. Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the Proceedings of Semiconductor Research Corporation (SRC) TECHCON, September 2015.
  5. Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2015, pp. 301--306.
  6. Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2015, pp. 283--288.
  7. Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2015, pp.1442--1445.
  8. Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON), April 2015, pp. 1--6.
  9. SynchroTrace new.jpg
    Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015), March 2015, pp. 278--287.
  10. Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, "Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping", Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID), January 2015, pp. 129--134.
  11. Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, "Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation", Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID), January 2015, pp. 135--140.
  12. Ying Teng and Baris Taskin, "Frequency-Centric Resonant Rotary Clock Distribution Network Design", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2014, pp. 742--749.
  13. Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2014, pp. 230--236.
  14. Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead "Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2014, pp. 517--520.
  15. Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2014, pp. 498--503.
  16. Julian Kemmerer and Baris Taskin, "Range-based Dynamic Routing of Hierarchical On Chip Network Traffic", Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)", June 2014, pp. 1-9.
  17. Ying Teng and Baris Taskin, "Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2013, pp. 479--482.
  18. Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE), June 2013, pp. 28--31.
  19. Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013, pp. 209--214.
  20. Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013, pp. 49--54. Best Paper Nominee.
  21. Ying Teng and Baris Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013, pp. 349--350.
  22. Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", Proceedings of Synopsys User Group Conference Silicon Valley (SNUG), March 2013.
  23. Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", Proceedings of the Design, Automation and Test in Europe (DATE), March 2013, pp. 1229--1234.
  24. Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2012, pp. 691--697.
  25. Matthew Guthaus and Baris Taskin, "High-Performance, Low-Power Resonant Clocking: Embedded tutorial", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2012, pp. 742--745.
  26. Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2012, pp. 201--206.
  27. Ying Teng and Baris Taskin, "Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2012, pp. 121--126.
  28. Ying Teng and Baris Taskin, "Synchronization Scheme for Brick-Based Rotary Oscillator Arrays", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2012, pp. 117--122.
  29. Ankit More and Baris Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2012, pp. 640--643.
  30. Vinayak Honkote, Ankit More and Baris Taskin, "3-D Parasitic Modeling for Rotary Interconnects", Proceedings of the International Conference on VLSI Design (VLSID), January 2012, pp. 137--142.
  31. Ankit More and Baris Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2011, pp. 19-24.
  32. Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2011, pp. 273--278.
  33. Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC", Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP), June 2011.
  34. Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE), June 2011, pp. 72--75.
  35. Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2011, pp. 1219--1222.
  36. Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2011, pp 1940--1943.
  37. Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2011, pp. 236--242.
  38. Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", Proceedings of the ACM International Symposium on Physical Design (ISPD), March 2011, pp. 131--138.
  39. Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", Proceedings of the Design, Automation and Test in Europe (DATE), March 2011, pp. 455--460.
  40. Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2010, pp. 209--214.
  41. Ankit More and Baris Taskin, "Wireless Interconnects for Inter-tier Communication on 3-D ICs", Proceedings of the European Microwave Integrated Circuits Conference (EuMIC), September 2010, pp. 105--108.
  42. Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC", Proceedings of the IEEE International SoC Conference (SOCC), September 2010, pp. 447--452.
  43. Ankit More and Baris Taskin, "Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits", Proceedings of the Mediterranean Microwave Symposium (MMS), August 2010.
  44. Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), August 2010, pp. 111--116.
  45. Ankit More and Baris Taskin, "Electromagnetic Compatibility of CMOS On-chip Antennas", Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation, July 2010, pp. 1--4.
  46. Ankit More and Baris Taskin, "Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2010, pp. 228-231.
  47. Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2010, pp.17-22.
  48. Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2010, pp. 471--472.
  49. Ankit More and Baris Taskin, "Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation", Proceedings of the System Level Interconnect Prediction (SLIP), June 2010, pp. 35--41.
  50. Ankit More and Baris Taskin, "Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects", Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI), May 2010, pp. 413-416.
  51. Ankit More and Baris Taskin, "Leakage Current Analysis for Intra-Chip Wireless Interconnects", Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2010, pp. 49--53.
  52. Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2010, pp. 765--770.
  53. Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2010, pp. 413--417.
  54. Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", Proceedings of the International Conference on VLSI Design (VLSID), January 2010, pp. 218--223.
  55. Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", Proceedings of the IEEE International SoC Design Conference (ISOCC), November 2009, pp. 232--236.
  56. Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", Proceedings of the IEEE International SoC Design Conference (ISOCC), November 2009, pp. 165--168.
  57. Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2009, pp. 224--227.
  58. Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies", Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2009, pp. 1147--1150.
  59. Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2009, pp. 232--235.
  60. Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2009, pp. 588--593.
  61. Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2008, pp. 114--119.
  62. Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2008, pp. 81--84.
  63. Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2008, pp. 605--608 Best student paper award nominee.
  64. Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2008, pp. 442--445.
  65. Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), October 2007, pp. 54--61.
  66. Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", Proceedings of the International Conference on Microelectronic Systems Education (MSE), June 2007, pp. 65--66.
  67. Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), August 2006, pp. 486--490.
  68. Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), August 2006, pp. 261--265.
  69. Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO), July 2006, pp. 302--305.
  70. Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", Proceedings of the ACM International Symposium on Physical Design (ISPD), Apr. 2005, pp. 47--54.
  71. Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2004, pp. 607--610.
  72. Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2004, pp. 603--606.
  73. Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2004, Vol. 2, pp. II-617--620.
  74. Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), December 2002, pp. 111--117.
  75. Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", Proceedings of the IEEE International ASIC/SOC Conference, September 2002, pp. 358--362.

Journals

  1. Ankit More and Baris Taskin, "Locality-Aware Network Utilization Balancing in NoCs", ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 21, No. 1, Article 6, November 2015.
  2. Ying Teng and Baris Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), Vol. 23, No. 11, pp. 2519--2530, November 2015.
  3. Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ACM Journal of Emerging Technologies in Computing Systems (JETC), Vol. 12, No. 2, Article 13, August 2015.
  4. Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", Elsevier Integration, The VLSI Journal, Vol. 47, No. 3, pp. 356--364, June 2014.
  5. Vinayak Honkote and Baris Taskin, "ZeROA: Zero Clock Skew Rotary Oscillatory Array", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), Vol. 20, No. 8, pp. 1528--1532, August 2012.
  6. Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), Vol. 20, No. 6, pp. 1002--1011, June 2012.
  7. Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 2, pp. 217--227, February 2012.
  8. Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 16, No. 4, Article 49, October 2011.
  9. Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), Vol. 19, No. 10, pp. 1837--1847, October 2011.
  10. Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", International Journal of Circuits, Systems and Computers (JCSC), Vol. 20, No. 5, pp. 881--898, 2011.
  11. Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", Special Issue: Journal of Selected Areas in Microelectronics (JSAM), December 2010, ISSN: 1925-2676.
  12. JOLPEDec10 small.jpg
    Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", Journal of Low Power Electronics (JOLPE), Vol. 6, No. 4, pp. 491--502, December 2010, Cover feature.
  13. Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", Journal of VLSI Design, Volume 2010 (2010), Article ID 451809.
  14. Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", International Journal on Circuits, Systems and Computers (JCSC), Vol. 18, No. 5, pp. 899--908, July 2009.
  15. Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 14, No. 3, Article 44, May 2009.
  16. Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ACM Journal on Emerging Technologies and Computation (JETC), Vol. 5, No. 1, Article 4, January 2009.
  17. Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), Vol. 16, No. 12, pp. 1648--1656, December 2008.
  18. Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 4, pp. 651--663, April 2006.
  19. Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), Vol. 12, No. 1, pp. 12--27, January 2004.

Books and Book Chapters

  1. Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, Timing Optimization through Clock Skew Scheduling, Springer, 2009, ISBN-13: 978-0387710556.
  2. Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, System Timing, Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.


  • Springer link [1]

    Springer link [1]

  • Amazon link [2]

    Amazon link [2]


Tutorials

  • Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).
  • High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).

Thesis and Dissertations

  • A. Can Sitik, Ph.D. Dissertation: Design and Automation of Voltage-Scaled Clock Networks, 2015
  • Ying Teng, Ph.D. Dissertation: Low Power Resonant Rotary Global Clock Distribution Network Design, 2014
  • Ankit More, Ph.D. Dissertation: Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs), 2013
  • Jianchao Lu, Ph.D. Dissertation, High Performance IC Clock Networks with Mesh and Tree Topologies, 2011
  • Vinayak Honkote, Ph.D. Dissertation, Design Automation and Analysis of Resonant Clocking Technologies, 2010
  • Shannon M. Kurtas, M.S. Thesis, Statistical Static Timing Analysis of Nonzero Clock Skew Circuits, 2007
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