Publications

Books and Book Chapters

1. Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, Timing Optimization through Clock Skew Scheduling, Springer, 2009, ISBN-13: 978-0387710556.
2. Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, System Timing, Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

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  Springer link [1]

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  Amazon link [2]

Journals

1. Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ACM Transactions on Design Automation of Electronic Systems (TODAES) (in pre-print).
2. Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (in pre-print).
3. Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", International Journal of Circuits, Systems and Computers (JCSC) (in pre-print).
4. Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", Special Issue: Journal of Selected Areas in Microelectronics (JSAM), December 2010, ISSN: 1925-2676.
5. 
   Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", Journal of Low Power Electronics (JOLPE), Vol. 6, No. 4, pp.491--502, December 2010, Cover feature.
6. Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", Journal of VLSI Design, Volume 2010 (2010), Article ID 451809.
7. Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", International Journal on Circuits, Systems and Computers (JCSC), Vol. 18, No. 5, pp. 899--908, July 2009.
8. Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 14, No. 3, Article 44, May 2009.
9. Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ACM Journal on Emerging Technologies and Computation (JETC), Vol. 5, No. 1, Article 4, January 2009.
10. Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 12, pp. 1648--1656, December 2008.
11. Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 4, pp. 651--663, April 2006.
12. Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 1, pp. 12--27, January 2004.

Conferences

1. Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", to appear in the "Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)", June 2011.
2. Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", to appear in the Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2011.
3. Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", to appear in the Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2011.
4. Sharat Shekar and Michael Bowen, "Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX", to appear in the Proceedings of Synopsys User Guide Conference San Jose(SNUG), March 2011.
5. Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", to appear in the Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2011.
6. Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", to appear in the Proceedings of the ACM International Symposium on Physical Design (ISPD), March 2011, pp. 131--138.
7. Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", Proceedings of the Design, Automation and Test in Europe (DATE), March 2011, pp. 455--460.
8. Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, "Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings", Proceedings of the International Conference on VLSI Design (VLSID), January 2011.
9. Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2010, pp. 209--214.
10. Ankit More and Baris Taskin, "Wireless Interconnects for Inter-tier Communication on 3-D ICs", Proceedings of the European Microwave Integrated Circuits Conference (EuMIC), September 2010, pp. 105--108.
11. Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC", Proceedings of the IEEE International SoC Conference (SOCC), September 2010.
12. Ankit More and Baris Taskin, "Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits", Proceedings of the Mediterranean Microwave Symposium (MMS), August 2010.
13. Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), August 2010, pp. 111--116.
14. Ankit More and Baris Taskin, "Electromagnetic Compatibility of CMOS On-chip Antennas", Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation, July 2010, pp. 1--4.
15. Ankit More and Baris Taskin, "Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2010, pp. 228-231.
16. Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2010, pp.17-22.
17. Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2010, pp. 471--472.
18. Ankit More and Baris Taskin, "Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation", Proceedings of the System Level Interconnect Prediction (SLIP), June 2010, pp. 35--41.
19. Ankit More and Baris Taskin, "Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects", Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI), May 2010, pp. 413-416.
20. Ankit More and Baris Taskin, "Leakage Current Analysis for Intra-Chip Wireless Interconnects", Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2010, pp. 49--53.
21. Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2010, pp. 765--770.
22. Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2010, pp. 413--417.
23. Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", Proceedings of the International Conference on VLSI Design (VLSID), January 2010, pp. 218--223.
24. Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", Proceedings of the IEEE International SoC Design Conference (ISOCC), November 2009, pp. 232--236.
25. Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", Proceedings of the IEEE International SoC Design Conference (ISOCC), November 2009, pp. 165--168.
26. Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2009, pp. 224--227.
27. Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies", Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2009, pp. 1147--1150.
28. Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2009, pp. 232--235.
29. Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2009, pp. 588--593.
30. Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2008, pp. 114--119.
31. Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2008, pp. 81--84.
32. Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2008, pp. 605--608 Best student paper award nominee.
33. Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2008, pp. 442--445.
34. Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), October 2007, pp. 54--61.
35. Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", Proceedings of the International Conference on Microelectronic Systems Education (MSE), June 2007, pp. 65--66.
36. Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), August 2006, pp. 486--490.
37. Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), August 2006, pp. 261--265.
38. Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO), July 2006, pp. 302--305.
39. Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", Proceedings of the ACM International Symposium on Physical Design (ISPD), Apr. 2005, pp. 47--54.
40. Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2004, pp. 607--610.
41. Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2004, pp. 603--606.
42. Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2004, Vol. 2, pp. II-617--620.
43. Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), December 2002, pp. 111--117.
44. Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", Proceedings of the IEEE International ASIC/SOC Conference, September 2002, pp. 358--362.

Thesis and Dissertations

• Vinayak Honkote, Ph.D. Dissertation, Design Automation and Analysis of Resonant Clocking Technologies, 2010

• Shannon M. Kurtas, M.S. Thesis, Statistical Static Timing Analysis of Nonzero Clock Skew Circuits, 2007